--- /srv/rebuilderd/tmp/rebuilderd30h85E/inputs/python3-slow5_1.3.1+dfsg-1_armhf.deb
+++ /srv/rebuilderd/tmp/rebuilderd30h85E/out/python3-slow5_1.3.1+dfsg-1_armhf.deb
├── file list
│ @@ -1,3 +1,3 @@
│  -rw-r--r--   0        0        0        4 2025-11-05 21:20:23.000000 debian-binary
│  -rw-r--r--   0        0        0     2148 2025-11-05 21:20:23.000000 control.tar.xz
│ --rw-r--r--   0        0        0  1479696 2025-11-05 21:20:23.000000 data.tar.xz
│ +-rw-r--r--   0        0        0  1480000 2025-11-05 21:20:23.000000 data.tar.xz
├── control.tar.xz
│ ├── control.tar
│ │ ├── ./md5sums
│ │ │ ├── ./md5sums
│ │ │ │┄ Files differ
├── data.tar.xz
│ ├── data.tar
│ │ ├── ./usr/lib/python3/dist-packages/pyslow5.cpython-313-arm-linux-gnueabihf.so
│ │ │┄ File has been modified after NT_GNU_BUILD_ID has been applied.
│ │ │ ├── readelf --wide --notes {}
│ │ │ │ @@ -1,4 +1,4 @@
│ │ │ │  
│ │ │ │  Displaying notes found in: .note.gnu.build-id
│ │ │ │    Owner                Data size 	Description
│ │ │ │ -  GNU                  0x00000014	NT_GNU_BUILD_ID (unique build ID bitstring)	    Build ID: daf9c751f0bb11e4abacb2f2fc34c66f4c1180bd
│ │ │ │ +  GNU                  0x00000014	NT_GNU_BUILD_ID (unique build ID bitstring)	    Build ID: 26471c33b5f538dbf61515dec900599e17434392
│ │ │ ├── objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}
│ │ │ │ @@ -2047,15 +2047,15 @@
│ │ │ │  	cmnlt	sp, r8, asr #25
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0004285
│ │ │ │  	blmi	fe8ea71c <slow5_exit_condition@@Base+0xfe838374>
│ │ │ │  	ldrbtmi	r4, [r9], #-2467	@ 0xfffff65d
│ │ │ │  	ldmdavs	r8, {r0, r1, r5, r6, r7, fp, ip, lr}
│ │ │ │  	bl	ff4483e0 <slow5_exit_condition@@Base+0xff396038>
│ │ │ │  	rscscc	pc, pc, pc, asr #32
│ │ │ │ -	ldmlt	sl!, {r0, r1, ip, sp, lr, pc}^
│ │ │ │ +	ldmlt	fp!, {r0, r1, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f4e9f
│ │ │ │  	stmdavs	r3, {r6, r9, lr}
│ │ │ │  	andls	r4, sp, lr, ror r4
│ │ │ │  	svclt	0x001c4293
│ │ │ │  	andvs	r3, r3, r1, lsl #6
│ │ │ │  	stcleq	8, cr15, [r8], {198}	@ 0xc6
│ │ │ │  	svc	0x0024f7fd
│ │ │ │ @@ -2147,15 +2147,15 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd3901
│ │ │ │  	mvnlt	lr, r2, asr sl
│ │ │ │  	svceq	0x0004f846
│ │ │ │  	stc	7, cr15, [ip, #-1012]!	@ 0xfffffc0c
│ │ │ │  	andsle	r3, r7, r1
│ │ │ │  	ldrb	r3, [r5, r8, lsl #14]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0034618
│ │ │ │ -	mcrmi	8, 2, fp, cr11, cr3, {1}
│ │ │ │ +	mcrmi	8, 2, fp, cr11, cr4, {1}
│ │ │ │  	ldc	6, cr4, [pc, #516]	@ a78c <ftello64@plt+0x23ac>
│ │ │ │  	ldrbtmi	r0, [lr], #-2867	@ 0xfffff4cd
│ │ │ │  	bl	fef48584 <slow5_exit_condition@@Base+0xfee961dc>
│ │ │ │  	beq	ff6488ac <slow5_exit_condition@@Base+0xff596504>
│ │ │ │  	cdp	1, 11, cr11, cr7, cr0, {2}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd0b00
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6ebb6
│ │ │ │ @@ -2171,15 +2171,15 @@
│ │ │ │  	stc2	0, cr15, [r2], #-20	@ 0xffffffec
│ │ │ │  			@ <UNDEFINED> instruction: 0x307cf89d
│ │ │ │  	ldrtmi	fp, [sl], -r3, lsr #2
│ │ │ │  	ldmdage	pc, {r0, r3, r5, r9, sl, lr}	@ <UNPREDICTABLE>
│ │ │ │  	bl	3485cc <slow5_exit_condition@@Base+0x296224>
│ │ │ │  			@ <UNDEFINED> instruction: 0x3078f89d
│ │ │ │  	strtmi	fp, [r9], -r3, lsr #2
│ │ │ │ -	ldmdage	lr, {r9, sp}
│ │ │ │ +	ldmdage	lr, {r0, r9, sp}
│ │ │ │  	ldcl	7, cr15, [lr, #-1012]!	@ 0xfffffc0c
│ │ │ │  	ldrbtmi	r4, [fp], #-2867	@ 0xfffff4cd
│ │ │ │  	stclcs	8, cr15, [r8], {211}	@ 0xd3
│ │ │ │  	ldmdavs	fp, {r1, r5, r6, r7, r8, ip, sp, pc}
│ │ │ │  			@ <UNDEFINED> instruction: 0x07f3b13b
│ │ │ │  	ldmdami	r0!, {r0, r2, r8, sl, ip, lr, pc}
│ │ │ │  	ldrtmi	r4, [r9], -r2, asr #12
│ │ │ │ @@ -2199,15 +2199,15 @@
│ │ │ │  	ldrbtmi	r4, [r9], #-2340	@ 0xfffff6dc
│ │ │ │  	ldmdavs	r8, {r0, r1, r5, r6, r7, fp, ip, lr}
│ │ │ │  	b	fe9c8634 <slow5_exit_condition@@Base+0xfe91628c>
│ │ │ │  	ldrbtmi	r4, [fp], #-2850	@ 0xfffff4de
│ │ │ │  	stcleq	8, cr15, [r8], {211}	@ 0xd3
│ │ │ │  			@ <UNDEFINED> instruction: 0xf080fab0
│ │ │ │  	submi	r0, r0, #64, 18	@ 0x100000
│ │ │ │ -	svclt	0x00caf002
│ │ │ │ +	svclt	0x00cbf002
│ │ │ │  	...
│ │ │ │  	muleq	sl, r0, r7
│ │ │ │  	andeq	r5, sl, r8, lsl #15
│ │ │ │  	andeq	r0, r0, r4, lsl #8
│ │ │ │  	andeq	r7, sl, r0, lsr r2
│ │ │ │  	andeq	r0, r0, r0, lsl r4
│ │ │ │  	andeq	sl, r7, lr, lsr #16
│ │ │ │ @@ -2518,274 +2518,274 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd4639
│ │ │ │  	strdlt	lr, [r0, #-146]!	@ 0xffffff6e
│ │ │ │  	stmdbvs	r4, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d6447e
│ │ │ │  			@ <UNDEFINED> instruction: 0xf00502fc
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6fa1f
│ │ │ │  	stmdacs	r0, {r2, r3, r4, r5, r6, r7, sl, fp}
│ │ │ │ -	strbhi	pc, [r3, #-2]	@ <UNPREDICTABLE>
│ │ │ │ +	strbhi	pc, [r4, #-2]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfe00b
│ │ │ │  			@ <UNDEFINED> instruction: 0x46393930
│ │ │ │  	ldrbtmi	r4, [fp], #-1584	@ 0xfffff9d0
│ │ │ │  	stclcs	8, cr15, [r8], {211}	@ 0xd3
│ │ │ │  	mrc	7, 3, APSR_nzcv, cr4, cr12, {7}
│ │ │ │  	blle	fe114b6c <slow5_exit_condition@@Base+0xfe0627c4>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d6e7e6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf005024c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6fa09
│ │ │ │  	stmdacs	r0, {r8, sl, fp}
│ │ │ │ -	strhi	pc, [sp, #-2]!
│ │ │ │ +	strhi	pc, [lr, #-2]!
│ │ │ │  	subseq	pc, r0, #14024704	@ 0xd60000
│ │ │ │  	blx	46b9c <PyInit_pyslow5@@Base+0x39484>
│ │ │ │  	ldcleq	8, cr15, [r4], #792	@ 0x318
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d68524
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d68525
│ │ │ │  			@ <UNDEFINED> instruction: 0xf00507ac
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6f9f7
│ │ │ │  	stmdacs	r0, {r2, r3, r5, r6, r7, sl, fp}
│ │ │ │ -	ldrhi	pc, [fp, #-2]
│ │ │ │ +	ldrhi	pc, [ip, #-2]
│ │ │ │  	beq	ff348f00 <slow5_exit_condition@@Base+0xff296b58>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf9eef005
│ │ │ │  	stceq	8, cr15, [r4, #-792]	@ 0xfffffce8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d68512
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d68513
│ │ │ │  			@ <UNDEFINED> instruction: 0xf005050c
│ │ │ │  	stmdacs	r0, {r0, r2, r5, r6, r7, r8, fp, ip, sp, lr, pc}
│ │ │ │ -	strhi	pc, [fp, #-2]
│ │ │ │ +	strhi	pc, [ip, #-2]
│ │ │ │  	cmppeq	r8, #14024704	@ p-variant is OBSOLETE	@ 0xd60000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf9def005
│ │ │ │  	ldcleq	8, cr15, [r4], {198}	@ 0xc6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d68502
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d68503
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0050644
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6f9d5
│ │ │ │  	stmdacs	r0, {r2, r3, r8, sl, fp}
│ │ │ │ -	ldrbthi	pc, [r9], #2	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbthi	pc, [sl], #2	@ <UNPREDICTABLE>
│ │ │ │  	msreq	SPSR_s, #14024704	@ 0xd60000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf9ccf005
│ │ │ │  	stcleq	8, cr15, [ip], {198}	@ 0xc6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d684f0
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d684f1
│ │ │ │  			@ <UNDEFINED> instruction: 0xf00501d8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6f9c3
│ │ │ │  	stmdacs	r0, {r2, r5, r6, r7, sl, fp}
│ │ │ │ -	strbthi	pc, [r7], #2	@ <UNPREDICTABLE>
│ │ │ │ +	strbthi	pc, [r8], #2	@ <UNPREDICTABLE>
│ │ │ │  	ldmdavs	ip!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d6447e
│ │ │ │  			@ <UNDEFINED> instruction: 0xf005020c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6f9b7
│ │ │ │  	stmdacs	r0, {r3, r4, r6, r7, sl, fp}
│ │ │ │ -	ldrbhi	pc, [fp], #2	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbhi	pc, [ip], #2	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0x063cf8d6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf9aef005
│ │ │ │  	ldcleq	8, cr15, [r0], {198}	@ 0xc6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d684d2
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d684d3
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0050238
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6f9a5
│ │ │ │  	stmdacs	r0, {r3, r4, r5, r6, r7, sl, fp}
│ │ │ │ -	strbhi	pc, [r9], #2	@ <UNPREDICTABLE>
│ │ │ │ +	strbhi	pc, [sl], #2	@ <UNPREDICTABLE>
│ │ │ │  	eorseq	pc, r0, #14024704	@ 0xd60000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf99cf005
│ │ │ │  	ldceq	8, cr15, [r0, #-792]	@ 0xfffffce8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf43f2800
│ │ │ │  	andcs	sl, r1, lr, lsl #30
│ │ │ │  	stmia	sl, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │  	tstpeq	r4, r6, asr #17	@ p-variant is OBSOLETE
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d684b8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d684b9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f2b50
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df4140
│ │ │ │ -	ldmdavs	r3, {r2, r3, r4, fp, ip, sp, lr}
│ │ │ │ -	addmi	r4, fp, #2130706432	@ 0x7f000000
│ │ │ │ +	ldmdavs	r3, {r2, r3, r4, fp, sp, lr}
│ │ │ │ +	addmi	r4, fp, #2113929216	@ 0x7e000000
│ │ │ │  	tstpeq	r0, pc, asr #32	@ p-variant is OBSOLETE
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0056013
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dffe6d
│ │ │ │ -	stmiapl	r6!, {r3, fp, ip, sp}^
│ │ │ │ -			@ <UNDEFINED> instruction: 0x46314632
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf7fd4630
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eac8
│ │ │ │ +	stmiapl	r7!, {r3, fp, ip, sp}^
│ │ │ │ +			@ <UNDEFINED> instruction: 0x4639463a
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fd4638
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eac8
│ │ │ │  	stmdacs	r0, {r4, r8}
│ │ │ │ -	ldrhi	pc, [fp], #2
│ │ │ │ -	blcc	1349004 <slow5_exit_condition@@Base+0x1296c5c>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d72003
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d72b44
│ │ │ │ +	ldrhi	pc, [ip], #2
│ │ │ │ +	blcc	1349000 <slow5_exit_condition@@Base+0x1296c58>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d62003
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d62b44
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd1b48
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb74
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb74
│ │ │ │  	stmdacs	r0, {r3, r4, r8}
│ │ │ │ -	strhi	pc, [sp], #2
│ │ │ │ -			@ <UNDEFINED> instruction: 0x46314632
│ │ │ │ +	strhi	pc, [lr], #2
│ │ │ │ +			@ <UNDEFINED> instruction: 0x4639463a
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd2002
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb6a
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb6a
│ │ │ │  	stmdacs	r0, {r2, r3, r4, r8}
│ │ │ │ -	strhi	pc, [r3], #2
│ │ │ │ +	strhi	pc, [r4], #2
│ │ │ │  			@ <UNDEFINED> instruction: 0x37c0f8df
│ │ │ │ -	andcs	r4, r2, r2, lsr r6
│ │ │ │ +	andcs	r4, r2, sl, lsr r6
│ │ │ │  	andhi	pc, r3, r4, asr r8	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd4641
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb5c
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb5c
│ │ │ │  	stmdacs	r0, {r5, r8}
│ │ │ │ -	ldrbthi	pc, [r5], #-2	@ <UNPREDICTABLE>
│ │ │ │ -	strbmi	r9, [r3], -r0, lsl #12
│ │ │ │ -	blcs	1049054 <slow5_exit_condition@@Base+0xf96cac>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d72004
│ │ │ │ +	ldrbthi	pc, [r6], #-2	@ <UNPREDICTABLE>
│ │ │ │ +	strbmi	r9, [r3], -r0, lsl #14
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d62004
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d62b40
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd1af0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb4e
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb4e
│ │ │ │  	stmdacs	r0, {r2, r5, r8}
│ │ │ │ -	strbthi	pc, [r7], #-2	@ <UNPREDICTABLE>
│ │ │ │ -	strbmi	r9, [r3], -r0, lsl #12
│ │ │ │ -	blcs	f49070 <slow5_exit_condition@@Base+0xe96cc8>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d72004
│ │ │ │ +	strbthi	pc, [r8], #-2	@ <UNPREDICTABLE>
│ │ │ │ +	strbmi	r9, [r3], -r0, lsl #14
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d62004
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d62b3c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd1af0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb40
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb40
│ │ │ │  	stmdacs	r0, {r3, r5, r8}
│ │ │ │ -	ldrbhi	pc, [r9], #-2	@ <UNPREDICTABLE>
│ │ │ │ -	bne	ff849088 <slow5_exit_condition@@Base+0xff796ce0>
│ │ │ │ +	ldrbhi	pc, [sl], #-2	@ <UNPREDICTABLE>
│ │ │ │ +	bne	ff849084 <slow5_exit_condition@@Base+0xff796cdc>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd2001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb36
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb36
│ │ │ │  	stmdacs	r0, {r2, r3, r5, r8}
│ │ │ │ -	strbhi	pc, [pc], #-2	@ ad3c <ftello64@plt+0x295c>	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbhi	pc, [r0], #-2	@ <UNPREDICTABLE>
│ │ │ │  	andcs	r4, r1, r1, asr #12
│ │ │ │  	bl	b48d38 <slow5_exit_condition@@Base+0xa96990>
│ │ │ │ -	teqpeq	r0, r7, asr #17	@ p-variant is OBSOLETE
│ │ │ │ +	teqpeq	r0, r6, asr #17	@ p-variant is OBSOLETE
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -	ldrtmi	r8, [r1], -r6, asr #8
│ │ │ │ +	ldrtmi	r8, [r9], -r7, asr #8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd2001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c7eb24
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c6eb24
│ │ │ │  	stmdacs	r0, {r2, r4, r5, r8}
│ │ │ │ -	ldrthi	pc, [sp], #-2	@ <UNPREDICTABLE>
│ │ │ │ -	bne	ff8490c0 <slow5_exit_condition@@Base+0xff796d18>
│ │ │ │ -	andcs	r4, r2, r2, lsr r6
│ │ │ │ +	ldrthi	pc, [lr], #-2	@ <UNPREDICTABLE>
│ │ │ │ +	bne	ff8490bc <slow5_exit_condition@@Base+0xff796d14>
│ │ │ │ +	andcs	r4, r2, sl, lsr r6
│ │ │ │  	bl	648d60 <slow5_exit_condition@@Base+0x5969b8>
│ │ │ │ -	teqpeq	r8, r7, asr #17	@ p-variant is OBSOLETE
│ │ │ │ +	teqpeq	r8, r6, asr #17	@ p-variant is OBSOLETE
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0022800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8df8432
│ │ │ │ -	ldrtmi	r7, [r3], -r4, lsr #14
│ │ │ │ -	ldrbtmi	r2, [pc], #-3	@ ad80 <ftello64@plt+0x29a0>
│ │ │ │ -	blcs	10490e0 <slow5_exit_condition@@Base+0xf96d38>
│ │ │ │ -	bne	ffc490e4 <slow5_exit_condition@@Base+0xffb96d3c>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8df8433
│ │ │ │ +	ldrtmi	r6, [fp], -r4, lsr #14
│ │ │ │ +	ldrbtmi	r2, [lr], #-3
│ │ │ │ +	blcs	10490dc <slow5_exit_condition@@Base+0xf96d34>
│ │ │ │ +	bne	ffc490e0 <slow5_exit_condition@@Base+0xffb96d38>
│ │ │ │  	bl	248d80 <slow5_exit_condition@@Base+0x1969d8>
│ │ │ │ -	teqpeq	ip, r7, asr #17	@ p-variant is OBSOLETE
│ │ │ │ +	teqpeq	ip, r6, asr #17	@ p-variant is OBSOLETE
│ │ │ │  			@ <UNDEFINED> instruction: 0xf43f2800
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7feae70
│ │ │ │  	andcc	pc, r1, r7, asr #22
│ │ │ │  	mcrge	4, 3, pc, cr11, cr15, {1}	@ <UNPREDICTABLE>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf06f6833
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c74240
│ │ │ │ -	addsmi	r6, r3, #20, 26	@ 0x500
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf06f683b
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c64240
│ │ │ │ +	addsmi	r7, r3, #20, 26	@ 0x500
│ │ │ │  	usatcs	pc, #16, pc, asr #17	@ <UNPREDICTABLE>
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │ -	ldrbtmi	r6, [sl], #-51	@ 0xffffffcd
│ │ │ │ -	usatvc	pc, #8, pc, asr #17	@ <UNPREDICTABLE>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8c2447f
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf06f6d18
│ │ │ │ +	ldrbtmi	r6, [sl], #-59	@ 0xffffffc5
│ │ │ │ +	usatvs	pc, #8, pc, asr #17	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8c2447e
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf06f7d18
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  			@ <UNDEFINED> instruction: 0x26dcf8df
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │ -	ldrbtmi	r6, [sl], #-51	@ 0xffffffcd
│ │ │ │ -	subeq	pc, ip, r7, lsl #2
│ │ │ │ -	ldcvs	8, cr15, [ip, #-776]	@ 0xfffffcf8
│ │ │ │ +	ldrbtmi	r6, [sl], #-59	@ 0xffffffc5
│ │ │ │ +	ldcvc	8, cr15, [ip, #-776]	@ 0xfffffcf8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df4293
│ │ │ │ -	svclt	0x001c26c8
│ │ │ │ -	eorsvs	r3, r3, r1, lsl #6
│ │ │ │ +	svclt	0x001c26cc
│ │ │ │ +	eorsvs	r3, fp, r1, lsl #6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c2447a
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf06f6d20
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf06f7d20
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │ -	ssatcs	pc, #21, pc, asr #17	@ <UNPREDICTABLE>
│ │ │ │ +	ssatcs	pc, #25, pc, asr #17	@ <UNPREDICTABLE>
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │ -	ldrbtmi	r6, [sl], #-51	@ 0xffffffcd
│ │ │ │ -	stcvs	8, cr15, [r4, #-776]!	@ 0xfffffcf8
│ │ │ │ +	ldrbtmi	r6, [sl], #-59	@ 0xffffffc5
│ │ │ │ +	stcvc	8, cr15, [r4, #-776]!	@ 0xfffffcf8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df4293
│ │ │ │ -	svclt	0x001c26a4
│ │ │ │ -	eorsvs	r3, r3, r1, lsl #6
│ │ │ │ +	svclt	0x001c26a8
│ │ │ │ +	eorsvs	r3, fp, r1, lsl #6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c2447a
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf06f6d28
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf06f7d28
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8df6033
│ │ │ │ -	ldrbtmi	r6, [lr], #-1676	@ 0xfffff974
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8df603b
│ │ │ │ +	ldrbtmi	r7, [pc], #-1680	@ ae2c <ftello64@plt+0x2a4c>
│ │ │ │ +	subeq	pc, ip, r7, lsl #2
│ │ │ │  	addseq	pc, r0, r6, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0xf932f7fe
│ │ │ │  	vmlal.s8	q9, d2, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d683ce
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d683cf
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d62090
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d61270
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd0cc8
│ │ │ │  	stmdacs	r0, {r1, r2, r4, fp, sp, lr, pc}
│ │ │ │ -	bichi	pc, r3, #536870924	@ 0x2000000c
│ │ │ │ +	bichi	pc, r4, #536870924	@ 0x2000000c
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d6
│ │ │ │  			@ <UNDEFINED> instruction: 0xf970f7ff
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf50783bc
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf50783bd
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6708e
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe0094
│ │ │ │  	stmdacs	r0, {r0, r1, r2, r4, r8, fp, ip, sp, lr, pc}
│ │ │ │ -			@ <UNDEFINED> instruction: 0x83b3f2c2
│ │ │ │ +			@ <UNDEFINED> instruction: 0x83b4f2c2
│ │ │ │  	rscsvc	pc, r6, r7, lsl #10
│ │ │ │  	addseq	pc, r8, r6, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0xf90ef7fe
│ │ │ │  	vmlal.s8	q9, d2, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf50783aa
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf50783ab
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6702f
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe009c
│ │ │ │  	stmdacs	r0, {r0, r2, r8, fp, ip, sp, lr, pc}
│ │ │ │ -			@ <UNDEFINED> instruction: 0x83a1f2c2
│ │ │ │ +			@ <UNDEFINED> instruction: 0x83a2f2c2
│ │ │ │  	rsbvc	pc, r3, r7, lsl #10
│ │ │ │  	adceq	pc, r0, r6, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8fcf7fe
│ │ │ │  	vmlal.s8	q9, d2, d0
│ │ │ │ -	vcge.s8	d8, d23, d8
│ │ │ │ +	vcge.s8	d8, d23, d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6405c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe00a4
│ │ │ │  	stmdacs	r0, {r0, r1, r4, r5, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │ -	orrhi	pc, pc, #536870924	@ 0x2000000c
│ │ │ │ +	orrshi	pc, r0, #536870924	@ 0x2000000c
│ │ │ │  	eorpl	pc, ip, r7, lsl #4
│ │ │ │  	adceq	pc, r8, r6, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8eaf7fe
│ │ │ │  	vmlal.s8	q9, d2, d0
│ │ │ │ -	vcgt.s8	d8, d23, d6
│ │ │ │ +	vcgt.s8	d8, d23, d7
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c650fc
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe00ac
│ │ │ │  	stmdacs	r0, {r0, r5, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │ -	cmnphi	sp, #536870924	@ p-variant is OBSOLETE	@ 0x2000000c
│ │ │ │ +	cmnphi	lr, #536870924	@ p-variant is OBSOLETE	@ 0x2000000c
│ │ │ │  	ldrbvs	pc, [r8, #2271]	@ 0x8df	@ <UNPREDICTABLE>
│ │ │ │  	ldrbvc	pc, [r8, #2271]	@ 0x8df	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df447e
│ │ │ │  	ldrbtmi	r3, [pc], #-1496	@ aef0 <ftello64@plt+0x2b10>
│ │ │ │  	sbcvs	pc, ip, r7, lsl #4
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c600b0
│ │ │ │  			@ <UNDEFINED> instruction: 0xf6063d2c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6532c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe3cf0
│ │ │ │  	stmdacs	r0, {r0, r3, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │ -	msrhi	SPSR_sc, #536870924	@ 0x2000000c
│ │ │ │ +	msrhi	SPSR_sx, #536870924	@ 0x2000000c
│ │ │ │  	ldclne	8, cr15, [r0], #856	@ 0x358
│ │ │ │  	ldrsbteq	pc, [r0], r6	@ <UNPREDICTABLE>
│ │ │ │  	blx	5c8f12 <slow5_exit_condition@@Base+0x516b6a>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d6835c
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d6835d
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe00b0
│ │ │ │  	andcc	pc, r1, r3, lsr r9	@ <UNPREDICTABLE>
│ │ │ │ -	cmpphi	r5, #2	@ p-variant is OBSOLETE
│ │ │ │ +	cmpphi	r6, #2	@ p-variant is OBSOLETE
│ │ │ │  	ldrsbteq	pc, [r0], r6	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf902f7ff
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -	vcgt.s8	q4, <illegal reg q3.5>, q7
│ │ │ │ +	vcgt.s8	q4, <illegal reg q3.5>, <illegal reg q7.5>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6709c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe00b4
│ │ │ │  	stmdacs	r0, {r0, r3, r5, r7, fp, ip, sp, lr, pc}
│ │ │ │ -	movthi	pc, #21186	@ 0x52c2	@ <UNPREDICTABLE>
│ │ │ │ +	movthi	pc, #25282	@ 0x62c2	@ <UNPREDICTABLE>
│ │ │ │  	ldrsbteq	pc, [r4], r6	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8f2f7ff
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8df833e
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8df833f
│ │ │ │  			@ <UNDEFINED> instruction: 0xf6073568
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6006c
│ │ │ │  	ldrbtmi	r0, [fp], #-184	@ 0xffffff48
│ │ │ │  	ldccc	8, cr15, [r0, #-792]!	@ 0xfffffce8
│ │ │ │  	ldrbcc	pc, [r8, #-2271]	@ 0xfffff721	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df3d34
│ │ │ │ @@ -2803,27 +2803,27 @@
│ │ │ │  	stclcc	8, cr15, [r8, #-792]	@ 0xfffffce8
│ │ │ │  	ldrcc	pc, [r4, #-2271]!	@ 0xfffff721
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf5063d4c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c66353
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe3cdc
│ │ │ │  	stmdacs	r0, {r0, r2, r3, r5, r6, fp, ip, sp, lr, pc}
│ │ │ │ -	movwhi	pc, #37570	@ 0x92c2	@ <UNPREDICTABLE>
│ │ │ │ +	movwhi	pc, #41666	@ 0xa2c2	@ <UNPREDICTABLE>
│ │ │ │  	ldclne	8, cr15, [ip], {214}	@ 0xd6
│ │ │ │  	ldrsbteq	pc, [r8], r6	@ <UNPREDICTABLE>
│ │ │ │  	blx	feec8fc8 <slow5_exit_condition@@Base+0xfee16c20>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d68300
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d68301
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fe00b8
│ │ │ │  	ldrdcc	pc, [r1], -r7
│ │ │ │ -	rscshi	pc, r9, #2
│ │ │ │ +	rscshi	pc, sl, #2
│ │ │ │  	ldrsbteq	pc, [r8], r6	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8a6f7ff
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8df82f2
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8df82f3
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df64f0
│ │ │ │  	ldrbtmi	lr, [lr], #-1264	@ 0xfffffb10
│ │ │ │  	ldrbvs	pc, [r5, -r6, lsl #10]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf60e44fe
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d61b3c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6ccdc
│ │ │ │  	ldm	ip!, {r3, r5, r6, r7, sl, fp, ip, sp, lr}
│ │ │ │ @@ -2839,23 +2839,23 @@
│ │ │ │  	ldrtcc	pc, [r8], #2271	@ 0x8df	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c6447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df3d68
│ │ │ │  	ldrbtmi	r3, [fp], #-1204	@ 0xfffffb4c
│ │ │ │  	stclcc	8, cr15, [ip, #-792]!	@ 0xfffffce8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf826f7fe
│ │ │ │  	vmlal.s8	q9, d2, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d682c2
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d682c3
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d61ce8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd00bc
│ │ │ │  	andcc	pc, r1, r3, ror sl	@ <UNPREDICTABLE>
│ │ │ │ -	adcshi	pc, r9, #2
│ │ │ │ +	adcshi	pc, sl, #2
│ │ │ │  	ldrsbteq	pc, [ip], r6	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf890f7fe
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0023001
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d682b2
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d682b3
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7ff00bc
│ │ │ │  	andcc	pc, r1, pc, asr r8	@ <UNPREDICTABLE>
│ │ │ │  	ldclge	4, cr15, [r9], #252	@ 0xfc
│ │ │ │  	ldrbthi	pc, [r4], #-2271	@ 0xfffff721	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0x464044f8
│ │ │ │  	svc	0x0020f7fc
│ │ │ │  	stmdacs	r0, {r0, r1, r2, r9, sl, lr}
│ │ │ │ @@ -2990,15 +2990,15 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0042701
│ │ │ │  	ldrbtmi	pc, [r8], #3513	@ 0xdb9	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7ff463e
│ │ │ │  	andcs	fp, lr, #136, 18	@ 0x220000
│ │ │ │  	ldmdage	sp, {r8, sp}
│ │ │ │  	mcr	7, 3, pc, cr4, cr12, {7}	@ <UNPREDICTABLE>
│ │ │ │  	mcr	7, 5, pc, cr6, cr12, {7}	@ <UNPREDICTABLE>
│ │ │ │ -	bllt	1be5dd0 <slow5_exit_condition@@Base+0x1b33a28>
│ │ │ │ +	bllt	1ae5dc0 <slow5_exit_condition@@Base+0x1a33a18>
│ │ │ │  	addshi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │  	stmibmi	r7!, {r0, r9, sp}
│ │ │ │  	ldrbtmi	r4, [r9], #-1272	@ 0xfffffb08
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd4640
│ │ │ │  			@ <UNDEFINED> instruction: 0x4605e872
│ │ │ │  			@ <UNDEFINED> instruction: 0xf43f2800
│ │ │ │  	bmi	fe8f6220 <slow5_exit_condition@@Base+0xfe843e78>
│ │ │ │ @@ -3010,15 +3010,15 @@
│ │ │ │  	orrvs	r7, r3, sl, lsl r2
│ │ │ │  	ldmdage	sp, {r0, r1, r2, r8, r9, sp}
│ │ │ │  	blge	645a24 <slow5_exit_condition@@Base+0x59367c>
│ │ │ │  	stcl	7, cr15, [r8, #1008]!	@ 0x3f0
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0003001
│ │ │ │  			@ <UNDEFINED> instruction: 0xf89d86ad
│ │ │ │  	teqlt	fp, r4, ror r0
│ │ │ │ -	ldmdage	sp, {r1, r3, r4, r5, r9, sl, lr}
│ │ │ │ +	andcs	sl, r1, #1900544	@ 0x1d0000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc4629
│ │ │ │  	andcc	lr, r1, r2, lsr ip
│ │ │ │  	strthi	pc, [r2], r0
│ │ │ │  	cdpge	15, 0, cr10, cr14, cr15, {0}
│ │ │ │  	ldmdaeq	r4!, {r0, r2, r3, r8, ip, sp, lr, pc}
│ │ │ │  	mrc	7, 3, APSR_nzcv, cr0, cr12, {7}
│ │ │ │  			@ <UNDEFINED> instruction: 0x4632463b
│ │ │ │ @@ -3115,20 +3115,20 @@
│ │ │ │  	andeq	r6, sl, r2, lsr #21
│ │ │ │  	strdeq	r6, [sl], -r0
│ │ │ │  	andeq	r6, sl, r8, lsl #19
│ │ │ │  	andeq	r0, r0, r8, asr r4
│ │ │ │  	andeq	r0, r0, r8, lsr r4
│ │ │ │  	andeq	r6, sl, r2, lsl #17
│ │ │ │  	andeq	r6, sl, sl, asr #16
│ │ │ │ -			@ <UNDEFINED> instruction: 0x000a53b4
│ │ │ │ +	andeq	r6, sl, r4, asr #16
│ │ │ │  	andeq	r6, sl, lr, lsr #16
│ │ │ │ -	andeq	r6, sl, r4, lsl r8
│ │ │ │ -	strdeq	r6, [sl], -lr
│ │ │ │ -	andeq	r6, sl, r8, ror #15
│ │ │ │ -	ldrdeq	r6, [sl], -r2
│ │ │ │ +	andeq	r6, sl, r8, lsl r8
│ │ │ │ +	andeq	r6, sl, r2, lsl #16
│ │ │ │ +	andeq	r6, sl, ip, ror #15
│ │ │ │ +	andeq	r5, sl, r6, asr #6
│ │ │ │  	andeq	r6, sl, r8, lsl r7
│ │ │ │  	andeq	r5, sl, r2, lsl #5
│ │ │ │  	andeq	sl, r0, r1, lsr #3
│ │ │ │  	andeq	r0, r2, fp, rrx
│ │ │ │  	andeq	r9, r1, r1, asr sp
│ │ │ │  	andeq	r7, r1, pc, asr pc
│ │ │ │  	andeq	r7, r1, sp, lsl fp
│ │ │ │ @@ -4110,20 +4110,20 @@
│ │ │ │  	ldmdavs	fp!, {r3, r4, r5, r6, sl, lr}
│ │ │ │  	rscscc	pc, ip, r0, lsl #12
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d7
│ │ │ │  	addne	pc, r0, #14090240	@ 0xd70000
│ │ │ │  	mcrr2	7, 15, pc, sl, cr12	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c84681
│ │ │ │  	stmdacs	r0, {}	@ <UNPREDICTABLE>
│ │ │ │ -	sbchi	pc, ip, r1
│ │ │ │ +	sbchi	pc, sp, r1
│ │ │ │  	ldrne	pc, [r8], #2263	@ 0x8d7
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d7464a
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc0090
│ │ │ │  	stmdacs	r0, {r0, r3, fp, ip, sp, lr, pc}
│ │ │ │ -	strhi	pc, [pc, -r0, asr #5]
│ │ │ │ +	ldrhi	pc, [r0, -r0, asr #5]
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c93b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb4648
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfeafe
│ │ │ │ @@ -4134,20 +4134,20 @@
│ │ │ │  	movwls	r3, #340	@ 0x154
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	addne	pc, r8, #14221312	@ 0xd90000
│ │ │ │  	ldc2	7, cr15, [sl], {252}	@ 0xfc
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c84607
│ │ │ │  	stmdacs	r0, {}	@ <UNPREDICTABLE>
│ │ │ │ -	ldrbthi	pc, [r0], r0	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbthi	pc, [r1], r0	@ <UNPREDICTABLE>
│ │ │ │  	strbne	pc, [r0, #2265]	@ 0x8d9	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d9463a
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r3, r4, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strbthi	pc, [sp], r0, asr #5	@ <UNPREDICTABLE>
│ │ │ │ +	strbthi	pc, [lr], r0, asr #5	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f683b
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	804c8 <slow5_ptr_depress_solo@@Base+0x230>
│ │ │ │  	ldmdblt	r3, {r0, r1, r3, r4, r5, sp, lr}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb4638
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfead0
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df9c54
│ │ │ │ @@ -4157,20 +4157,20 @@
│ │ │ │  	movwls	r3, #344	@ 0x158
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	addne	pc, r4, #14221312	@ 0xd90000
│ │ │ │  	blx	ffb4a4d6 <slow5_exit_condition@@Base+0xffa9812e>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c84607
│ │ │ │  	stmdacs	r0, {}	@ <UNPREDICTABLE>
│ │ │ │ -	ldrbhi	pc, [r0], r0	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbhi	pc, [r1], r0	@ <UNPREDICTABLE>
│ │ │ │  	strne	pc, [r4, #2265]!	@ 0x8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d9463a
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r1, r3, r5, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strbhi	pc, [sp], r0, asr #5	@ <UNPREDICTABLE>
│ │ │ │ +	strbhi	pc, [lr], r0, asr #5	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f683b
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80524 <slow5_ptr_depress_solo@@Base+0x28c>
│ │ │ │  	ldmdblt	r3, {r0, r1, r3, r4, r5, sp, lr}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb4638
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfeaa2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df9c00
│ │ │ │ @@ -4180,20 +4180,20 @@
│ │ │ │  	movwls	r3, #348	@ 0x15c
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	addsne	pc, r0, #14221312	@ 0xd90000
│ │ │ │  	blx	fefca532 <slow5_exit_condition@@Base+0xfef1818a>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c84607
│ │ │ │  	stmdacs	r0, {}	@ <UNPREDICTABLE>
│ │ │ │ -	ldrthi	pc, [r0], r0	@ <UNPREDICTABLE>
│ │ │ │ +	ldrthi	pc, [r1], r0	@ <UNPREDICTABLE>
│ │ │ │  	strbne	pc, [r8, #2265]!	@ 0x8d9	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d9463a
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r2, r3, r4, r5, r6, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strthi	pc, [sp], r0, asr #5
│ │ │ │ +	strthi	pc, [lr], r0, asr #5
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f683b
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80580 <slow5_ptr_depress@@Base+0x38>
│ │ │ │  	ldmdblt	r3, {r0, r1, r3, r4, r5, sp, lr}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb4638
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfea74
│ │ │ │  	svcge	0x00109bac
│ │ │ │ @@ -4203,20 +4203,20 @@
│ │ │ │  	ldrdcc	pc, [r0, #-137]!	@ 0xffffff77
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc128c
│ │ │ │  	strmi	pc, [r0], pc, lsl #23
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	ldrhi	pc, [r0], r0
│ │ │ │ +	ldrhi	pc, [r1], r0
│ │ │ │  	strbne	pc, [r8, #2265]	@ 0x8d9	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r1, r2, r3, r6, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strhi	pc, [sp], r0, asr #5
│ │ │ │ +	strhi	pc, [lr], r0, asr #5
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfea44
│ │ │ │ @@ -4227,20 +4227,20 @@
│ │ │ │  	movwls	r3, #356	@ 0x164
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	addsne	pc, r4, #14221312	@ 0xd90000
│ │ │ │  	blx	184a5ee <slow5_exit_condition@@Base+0x1798246>
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d9866f
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d98670
│ │ │ │  			@ <UNDEFINED> instruction: 0x464215f8
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xff20f7fb
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d8866c
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d8866d
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80640 <slow5_ptr_depress@@Base+0xf8>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	b	54a620 <slow5_exit_condition@@Base+0x498278>
│ │ │ │  	bls	fff4a9b4 <slow5_exit_condition@@Base+0xffe9860c>
│ │ │ │ @@ -4250,20 +4250,20 @@
│ │ │ │  	ldrdcc	pc, [r8, #-137]!	@ 0xffffff77
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12c8
│ │ │ │  			@ <UNDEFINED> instruction: 0x4680fb31
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	strbhi	pc, [lr], -r0	@ <UNPREDICTABLE>
│ │ │ │ +	strbhi	pc, [pc], -r0	@ <UNPREDICTABLE>
│ │ │ │  	ldrne	pc, [ip, #2265]!	@ 0x8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r4, r5, r6, r7, r9, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strbhi	pc, [fp], -r0, asr #5	@ <UNPREDICTABLE>
│ │ │ │ +	strbhi	pc, [ip], -r0, asr #5	@ <UNPREDICTABLE>
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfe9e6
│ │ │ │ @@ -4274,20 +4274,20 @@
│ │ │ │  	movwls	r3, #364	@ 0x16c
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	sbcsne	pc, r0, #14221312	@ 0xd90000
│ │ │ │  	blx	ca6aa <slow5_exit_condition@@Base+0x18302>
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d9862d
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d9862e
│ │ │ │  			@ <UNDEFINED> instruction: 0x464215d4
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d9
│ │ │ │  	mcr2	7, 6, pc, cr2, cr11, {7}	@ <UNPREDICTABLE>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d8862a
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d8862b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	806fc <slow5_ptr_depress@@Base+0x1b4>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	ldmib	r6!, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │  	bls	144aa70 <slow5_exit_condition@@Base+0x13986c8>
│ │ │ │ @@ -4297,27 +4297,27 @@
│ │ │ │  	ldrsbcc	pc, [r0, #-137]!	@ 0xffffff77	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12cc
│ │ │ │  	pkhtbmi	pc, r0, r3, asr #21	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	strhi	pc, [ip], -r0
│ │ │ │ +	strhi	pc, [sp], -r0
│ │ │ │  	ldrdcs	pc, [r0, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	bcc	54aab4 <slow5_exit_condition@@Base+0x49870c>
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	strbne	pc, [r4, #2259]	@ 0x8d3	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	mcr2	7, 4, pc, cr6, cr11, {7}	@ <UNPREDICTABLE>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d885fc
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d885fd
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80774 <slow5_ptr_depress@@Base+0x22c>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	ldmdb	sl!, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │  	stmibls	r4!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │ @@ -4327,27 +4327,27 @@
│ │ │ │  	ldrsbcc	pc, [r4, #-137]!	@ 0xffffff77	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12dc
│ │ │ │  	pkhbtmi	pc, r0, r7, lsl #21	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	ldrbhi	pc, [lr]	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbhi	pc, [pc]	@ c798 <ftello64@plt+0x43b8>	@ <UNPREDICTABLE>
│ │ │ │  	ldrdcs	pc, [r0, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	stmibcc	r8!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	stmdane	ip, {r0, r1, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	mcr2	7, 2, pc, cr10, cr11, {7}	@ <UNPREDICTABLE>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d885ce
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d885cf
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	807ec <slow5_ptr_depress@@Base+0x2a4>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	ldmdb	lr!, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │  	ldmdbls	r8!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │ @@ -4357,27 +4357,27 @@
│ │ │ │  	ldrsbcc	pc, [r8, #-137]!	@ 0xffffff77	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12e0
│ │ │ │  	pkhtbmi	pc, r0, fp, asr #20	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	ldrhi	pc, [r0, #0]!
│ │ │ │ +	ldrhi	pc, [r1, #0]!
│ │ │ │  	ldrdcs	pc, [r4, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	ldmdbcc	ip!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	ldmdane	r0, {r0, r1, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	mcr2	7, 0, pc, cr14, cr11, {7}	@ <UNPREDICTABLE>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d885a0
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d885a1
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80864 <slow5_ptr_depress@@Base+0x31c>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	stmdb	r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │  	stmdbls	ip, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │ @@ -4387,27 +4387,27 @@
│ │ │ │  	ldrsbcc	pc, [ip, #-137]!	@ 0xffffff77	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12d4
│ │ │ │  	pkhbtmi	pc, r0, pc, lsl #20	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	strhi	pc, [r2]
│ │ │ │ +	strhi	pc, [r3]
│ │ │ │  	ldrdcs	pc, [r0, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	ldmcc	r0, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	strbne	pc, [r0, #2259]!	@ 0x8d3	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	ldc2l	7, cr15, [r2, #1004]	@ 0x3ec
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d88572
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d88573
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	808dc <slow5_ptr_depress@@Base+0x394>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	stmia	r6, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │  	stmials	r0!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │ @@ -4417,27 +4417,27 @@
│ │ │ │  	ldrdcc	pc, [r0, r9]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12d8
│ │ │ │  	strmi	pc, [r0], r3, ror #19
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	ldrbhi	pc, [r4, #-0]	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbhi	pc, [r5, #-0]	@ <UNPREDICTABLE>
│ │ │ │  	ldrdcs	pc, [r8, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	stmdacc	r4!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	strbne	pc, [r4, #2259]!	@ 0x8d3	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	ldc2	7, cr15, [r6, #1004]	@ 0x3ec
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d88544
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d88545
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80954 <slow5_ptr_depress@@Base+0x40c>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	stm	sl, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │  	ldmdals	r4!, {r0, r1, r2, r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │ @@ -4448,20 +4448,20 @@
│ │ │ │  	movwls	r3, #388	@ 0x184
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	sbcne	pc, r0, #14221312	@ 0xd90000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf9a6f7fc
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d98525
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d98526
│ │ │ │  			@ <UNDEFINED> instruction: 0x464215b0
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d9
│ │ │ │  	stc2l	7, cr15, [r6, #-1004]!	@ 0xfffffc14
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d88522
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d88523
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	809b4 <slow5_ptr_depress@@Base+0x46c>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	ldmda	sl, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0x97dcf8df
│ │ │ │ @@ -4471,27 +4471,27 @@
│ │ │ │  	ldrdcc	pc, [r8, r9]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12c4
│ │ │ │  			@ <UNDEFINED> instruction: 0x4680f977
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	strhi	pc, [r4, #-0]
│ │ │ │ +	strhi	pc, [r5, #-0]
│ │ │ │  	ldrdcs	pc, [ip, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	sbfxcc	pc, pc, #17, #1
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	ldrne	pc, [r4, #2259]!	@ 0x8d3
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	stc2	7, cr15, [sl, #-1004]!	@ 0xfffffc14
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d884f4
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d884f5
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80a2c <slow5_fwrite_compress@@Base+0x40>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	ldmda	lr, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │  			@ <UNDEFINED> instruction: 0x9770f8df
│ │ │ │ @@ -4501,27 +4501,27 @@
│ │ │ │  	ldrdcc	pc, [ip, r9]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12a8
│ │ │ │  			@ <UNDEFINED> instruction: 0x4680f93b
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	ldrbhi	pc, [r6], #0	@ <UNPREDICTABLE>
│ │ │ │ +	ldrbhi	pc, [r7], #0	@ <UNPREDICTABLE>
│ │ │ │  	ldrdcs	pc, [ip, -r9]!
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  			@ <UNDEFINED> instruction: 0x3734f8df
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  	ldrbne	pc, [r4, #-2259]!	@ 0xfffff72d	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	stc2l	7, cr15, [lr], #1004	@ 0x3ec
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d884c6
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d884c7
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80aa4 <slow5_fwrite_compress@@Base+0xb8>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	svc	0x00e2f7fa
│ │ │ │  			@ <UNDEFINED> instruction: 0x9704f8df
│ │ │ │ @@ -4531,20 +4531,20 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0x3190f8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12b0
│ │ │ │  			@ <UNDEFINED> instruction: 0x4680f8ff
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	strthi	pc, [r8], #0
│ │ │ │ +	strthi	pc, [r9], #0
│ │ │ │  	strne	pc, [r0, #2265]	@ 0x8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r1, r2, r3, r4, r5, r7, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strthi	pc, [r5], #704	@ 0x2c0
│ │ │ │ +	strthi	pc, [r6], #704	@ 0x2c0
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfefb4
│ │ │ │ @@ -4555,20 +4555,20 @@
│ │ │ │  	movwls	r3, #404	@ 0x194
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	adcsne	pc, r4, #14221312	@ 0xd90000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d0f7fc
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d98487
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d98488
│ │ │ │  			@ <UNDEFINED> instruction: 0x46421590
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d9
│ │ │ │  	ldc2	7, cr15, [r0], {251}	@ 0xfb
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d88484
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d88485
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80b60 <slow5_fwrite_compress@@Base+0x174>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	svc	0x0084f7fa
│ │ │ │  			@ <UNDEFINED> instruction: 0x9658f8df
│ │ │ │ @@ -4578,20 +4578,20 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0x3198f8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc12ac
│ │ │ │  	strmi	pc, [r0], r1, lsr #17
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	strbthi	pc, [r6], #-0	@ <UNPREDICTABLE>
│ │ │ │ +	strbthi	pc, [r7], #-0	@ <UNPREDICTABLE>
│ │ │ │  	ldrbne	pc, [r8, #-2265]!	@ 0xfffff727	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r5, r6, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	strbthi	pc, [r3], #-704	@ 0xfffffd40	@ <UNPREDICTABLE>
│ │ │ │ +	strbthi	pc, [r4], #-704	@ 0xfffffd40	@ <UNPREDICTABLE>
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfef56
│ │ │ │ @@ -4602,26 +4602,26 @@
│ │ │ │  	movwls	r3, #412	@ 0x19c
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	adcsne	pc, r8, #14221312	@ 0xd90000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf872f7fc
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d98445
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d98446
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f2130
│ │ │ │  	strbvs	r4, [r2], #-320	@ 0xfffffec0
│ │ │ │  	addmi	r6, fp, #1245184	@ 0x130000
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df6013
│ │ │ │  	strmi	r3, [r2], -r8, asr #11
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d315a8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r2, r5, sl, fp, ip, sp, lr, pc}
│ │ │ │ -	ldrthi	pc, [r5], #-704	@ 0xfffffd40	@ <UNPREDICTABLE>
│ │ │ │ +	ldrthi	pc, [r6], #-704	@ 0xfffffd40	@ <UNPREDICTABLE>
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfef1a
│ │ │ │ @@ -4632,26 +4632,26 @@
│ │ │ │  	movwls	r3, #416	@ 0x1a0
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	adcsne	pc, ip, #14221312	@ 0xd90000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf836f7fc
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d98417
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d98418
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f2130
│ │ │ │  	strbvs	r4, [r2], #-320	@ 0xfffffec0
│ │ │ │  	addmi	r6, fp, #1245184	@ 0x130000
│ │ │ │  	movwcc	fp, #7964	@ 0x1f1c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8df6013
│ │ │ │  			@ <UNDEFINED> instruction: 0x4602355c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d315ac
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r3, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc}
│ │ │ │ -	strhi	pc, [r7], #-704	@ 0xfffffd40
│ │ │ │ +	strhi	pc, [r8], #-704	@ 0xfffffd40
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfeede
│ │ │ │ @@ -4662,20 +4662,20 @@
│ │ │ │  	movwls	r3, #420	@ 0x1a4
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	addsne	pc, r8, #14221312	@ 0xd90000
│ │ │ │  			@ <UNDEFINED> instruction: 0xfffaf7fb
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d983e9
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d983ea
│ │ │ │  			@ <UNDEFINED> instruction: 0x46421618
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d9
│ │ │ │  	blx	feecacce <slow5_exit_condition@@Base+0xfee18926>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d883e6
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d883e7
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80d0c <slow5_fwrite_compress@@Base+0x320>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	mcr	7, 5, pc, cr14, cr10, {7}	@ <UNPREDICTABLE>
│ │ │ │  	ldrbls	pc, [r4], #2271	@ 0x8df	@ <UNPREDICTABLE>
│ │ │ │ @@ -4686,20 +4686,20 @@
│ │ │ │  	movwls	r3, #424	@ 0x1a8
│ │ │ │  	ldrdcc	pc, [r0], -r9
│ │ │ │  			@ <UNDEFINED> instruction: 0x2784f8d9
│ │ │ │  	rsbsne	pc, ip, #14221312	@ 0xd90000
│ │ │ │  			@ <UNDEFINED> instruction: 0xffcaf7fb
│ │ │ │  	eorsvs	r4, r8, r0, lsl #13
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0002800
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d983c7
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d983c8
│ │ │ │  			@ <UNDEFINED> instruction: 0x464213f4
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d9
│ │ │ │  	blx	fe2cad2e <slow5_exit_condition@@Base+0xfe218986>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d883c4
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d883c5
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80d6c <slow5_fwrite_compress@@Base+0x380>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	mrc	7, 3, APSR_nzcv, cr14, cr10, {7}
│ │ │ │  	ldrbtls	pc, [ip], #-2271	@ 0xfffff721	@ <UNPREDICTABLE>
│ │ │ │ @@ -4709,27 +4709,27 @@
│ │ │ │  	ldrdcc	pc, [ip, r9]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb12a0
│ │ │ │  	pkhbtmi	pc, r0, fp, lsl #31	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -			@ <UNDEFINED> instruction: 0x83a6f000
│ │ │ │ +			@ <UNDEFINED> instruction: 0x83a7f000
│ │ │ │  	teqpcs	r4, r9	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	strbcc	pc, [r0], #-2271	@ 0xfffff721	@ <UNPREDICTABLE>
│ │ │ │  	ldrbtmi	r4, [fp], #-1538	@ 0xfffff9fe
│ │ │ │  			@ <UNDEFINED> instruction: 0x17dcf8d3
│ │ │ │  			@ <UNDEFINED> instruction: 0x0090f8d3
│ │ │ │  	blx	13cada6 <slow5_exit_condition@@Base+0x13189fe>
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8d88396
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8d88397
│ │ │ │  			@ <UNDEFINED> instruction: 0xf06f3000
│ │ │ │  	addsmi	r4, r3, #64, 4
│ │ │ │  	blcc	80de4 <slow5_fread_depress@@Base+0x48>
│ │ │ │  	andcc	pc, r0, r8, asr #17
│ │ │ │  			@ <UNDEFINED> instruction: 0x4640b913
│ │ │ │  	mcr	7, 2, pc, cr2, cr10, {7}	@ <UNPREDICTABLE>
│ │ │ │  	ldrls	pc, [r0], #-2271	@ 0xfffff721
│ │ │ │ @@ -4739,26 +4739,26 @@
│ │ │ │  	asrscc	pc, r9	@ <illegal shifter operand>	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb129c
│ │ │ │  	pkhtbmi	pc, r0, pc, asr #30	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	cmnphi	r8, #0	@ p-variant is OBSOLETE
│ │ │ │ +	cmnphi	r9, #0	@ p-variant is OBSOLETE
│ │ │ │  	teqpcs	r4, r9	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  			@ <UNDEFINED> instruction: 0x46024bf5
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d316b4
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r1, r4, r8, r9, fp, ip, sp, lr, pc}
│ │ │ │ -	msrhi	SPSR_fc, #192, 4
│ │ │ │ +	msrhi	SPSR_fx, #192, 4
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfee08
│ │ │ │ @@ -4768,26 +4768,26 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0x31b4f8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb12e4
│ │ │ │  	strmi	pc, [r0], r5, lsr #30
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	movthi	pc, #49152	@ 0xc000	@ <UNPREDICTABLE>
│ │ │ │ +	movthi	pc, #53248	@ 0xd000	@ <UNPREDICTABLE>
│ │ │ │  	teqpcs	r8, r9	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  			@ <UNDEFINED> instruction: 0x46024bdb
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3198c
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r3, r4, r6, r7, r9, fp, ip, sp, lr, pc}
│ │ │ │ -	teqphi	sp, #192, 4	@ p-variant is OBSOLETE
│ │ │ │ +	teqphi	lr, #192, 4	@ p-variant is OBSOLETE
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfedce
│ │ │ │ @@ -4797,26 +4797,26 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0x31b8f8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb12e8
│ │ │ │  	strmi	pc, [r0], fp, ror #29
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	nophi	{0}
│ │ │ │ +	msrhi	CPSR_c, #0
│ │ │ │  	teqpcs	r4, r9	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	strmi	r4, [r2], -r1, asr #23
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d319b4
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r1, r2, r3, r4, r7, r9, fp, ip, sp, lr, pc}
│ │ │ │ -	tstphi	r1, #192, 4	@ p-variant is OBSOLETE
│ │ │ │ +	tstphi	r2, #192, 4	@ p-variant is OBSOLETE
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfed94
│ │ │ │ @@ -4826,26 +4826,26 @@
│ │ │ │  			@ <UNDEFINED> instruction: 0x31bcf8d9
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb12ec
│ │ │ │  			@ <UNDEFINED> instruction: 0x4680feb1
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	rscshi	pc, r4, #0
│ │ │ │ +	rscshi	pc, r5, #0
│ │ │ │  	teqpcs	ip, r9	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │  	cmppmi	r0, pc, rrx	@ p-variant is OBSOLETE
│ │ │ │  	ldmdavs	r3, {r1, r6, sl, sp, lr}
│ │ │ │  	svclt	0x001c428b
│ │ │ │  	andsvs	r3, r3, r1, lsl #6
│ │ │ │  	strmi	r4, [r2], -r7, lsr #23
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d319cc
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r2, r5, r6, r9, fp, ip, sp, lr, pc}
│ │ │ │ -	rschi	pc, r5, #192, 4
│ │ │ │ +	rschi	pc, r6, #192, 4
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfed5a
│ │ │ │ @@ -4855,20 +4855,20 @@
│ │ │ │  	ldrdcc	pc, [r0, #137]	@ 0x89
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb12a4
│ │ │ │  			@ <UNDEFINED> instruction: 0x4680fe77
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	sbchi	pc, r8, #0
│ │ │ │ +	sbchi	pc, r9, #0
│ │ │ │  	ldrbtne	pc, [ip], #-2265	@ 0xfffff727	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0090
│ │ │ │  	stmdacs	r0, {r0, r1, r2, r4, r5, r9, fp, ip, sp, lr, pc}
│ │ │ │ -	sbchi	pc, r5, #192, 4
│ │ │ │ +	sbchi	pc, r6, #192, 4
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfed2c
│ │ │ │ @@ -4878,20 +4878,20 @@
│ │ │ │  	ldrdcc	pc, [r4, #137]	@ 0x89
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb1274
│ │ │ │  	strmi	pc, [r0], r9, asr #28
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	adchi	pc, r8, #0
│ │ │ │ +	adchi	pc, r9, #0
│ │ │ │  	stmdane	ip, {r0, r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0000
│ │ │ │  	stmdacs	r0, {r4, r7, fp, sp, lr, pc}
│ │ │ │ -	adchi	pc, r4, #192, 4
│ │ │ │ +	adchi	pc, r5, #192, 4
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8dfecfe
│ │ │ │ @@ -4901,36 +4901,36 @@
│ │ │ │  	ldrdcc	pc, [r8, #137]	@ 0x89
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d99300
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d93000
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d92784
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb1278
│ │ │ │  	pkhbtmi	pc, r0, fp, lsl #28	@ <UNPREDICTABLE>
│ │ │ │  	stmdacs	r0, {r3, r4, r5, sp, lr}
│ │ │ │ -	addhi	pc, r6, #0
│ │ │ │ +	addhi	pc, r7, #0
│ │ │ │  	stmdane	ip!, {r0, r3, r4, r6, r7, fp, ip, sp, lr, pc}^
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d94642
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fb0000
│ │ │ │  	stmdacs	r0, {r1, r5, r6, fp, sp, lr, pc}
│ │ │ │ -	addhi	pc, r2, #192, 4
│ │ │ │ +	addhi	pc, r3, #192, 4
│ │ │ │  	ldrdcc	pc, [r0], -r8
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r6, r3, r2
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8c83b01
│ │ │ │  	ldmdblt	r3, {ip, sp}
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fa4640
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7faecd0
│ │ │ │  	strmi	lr, [r7], -r8, asr #31
│ │ │ │  	stmdacs	r0, {r4, ip, pc}
│ │ │ │ -	rsbshi	pc, r4, #0
│ │ │ │ +	rsbshi	pc, r5, #0
│ │ │ │  			@ <UNDEFINED> instruction: 0x46024b59
│ │ │ │  			@ <UNDEFINED> instruction: 0xf8d3447b
│ │ │ │  	ldmdavs	r8, {r2, r3, r4, r8, fp, ip}
│ │ │ │  	stmda	r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │  	vmlal.s8	q9, d0, d0
│ │ │ │ -	ldmdavs	fp!, {r0, r1, r2, r3, r5, r6, r9, pc}
│ │ │ │ +	ldmdavs	fp!, {r4, r5, r6, r9, pc}
│ │ │ │  	submi	pc, r0, #111	@ 0x6f
│ │ │ │  	mulle	r5, r3, r2
│ │ │ │  	eorsvs	r3, fp, r1, lsl #22
│ │ │ │  			@ <UNDEFINED> instruction: 0x4638b913
│ │ │ │  	ldc	7, cr15, [r2], #1000	@ 0x3e8
│ │ │ │  			@ <UNDEFINED> instruction: 0x3076f89d
│ │ │ │  	andsls	r2, r0, #0, 4
│ │ │ │ @@ -5012,322 +5012,322 @@
│ │ │ │  	muleq	sl, r8, r5
│ │ │ │  	andeq	r3, sl, r6, lsl #2
│ │ │ │  	andeq	r4, sl, r0, lsr r5
│ │ │ │  	stc	7, cr15, [lr], #1000	@ 0x3e8
│ │ │ │  			@ <UNDEFINED> instruction: 0xf0024628
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fdfde5
│ │ │ │  	blmi	ffc3ba3c <slow5_exit_condition@@Base+0xffb89694>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf10d4629
│ │ │ │ -	stmiapl	r3!, {r1, r2, r4, r5, r6}^
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf7fa9307
│ │ │ │ -	andcc	lr, r1, r6, lsr pc
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfd1ee
│ │ │ │ -			@ <UNDEFINED> instruction: 0x270183b0
│ │ │ │ +	strtmi	r2, [r9], -r1, lsl #4
│ │ │ │ +	rsbseq	pc, r6, sp, lsl #2
│ │ │ │ +	movwls	r5, #30947	@ 0x78e3
│ │ │ │ +	svc	0x0034f7fa
│ │ │ │ +	mvnle	r3, r1
│ │ │ │ +			@ <UNDEFINED> instruction: 0x83acf8df
│ │ │ │ +	ldrbtmi	r2, [r8], #1793	@ 0x701
│ │ │ │ +	stmiblt	r5!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +			@ <UNDEFINED> instruction: 0x83a4f8df
│ │ │ │ +	strbvc	pc, [ip, pc, asr #8]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb9a6
│ │ │ │ -	vst2.32	{d24-d27}, [pc :128], r8
│ │ │ │ -	ldrbtmi	r7, [r8], #1996	@ 0x7cc
│ │ │ │ -	ldmiblt	pc, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}	@ <UNPREDICTABLE>
│ │ │ │ -	orrshi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb99e
│ │ │ │ +	vcge.s8	d24, d16, d12
│ │ │ │ +	ldrbtmi	r1, [r8], #1969	@ 0x7b1
│ │ │ │ +	ldmiblt	r7, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	orrshi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │  	ldrne	pc, [r1, r0, asr #4]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb998
│ │ │ │ -	vcge.s8	d24, d16, d4
│ │ │ │ -	ldrbtmi	r1, [r8], #1969	@ 0x7b1
│ │ │ │ -	ldmiblt	r1, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	orrhi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb990
│ │ │ │ +	vst2.32	{d24-d27}, [pc], r8
│ │ │ │ +	ldrbtmi	r7, [r8], #1796	@ 0x704
│ │ │ │ +	stmiblt	r9, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	cmnphi	ip, #14614528	@ p-variant is OBSOLETE	@ 0xdf0000
│ │ │ │  	strvc	pc, [r4, -pc, asr #8]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb98a
│ │ │ │ -	vst2.32	{d24-d27}, [pc], r0
│ │ │ │ -	ldrbtmi	r7, [r8], #1796	@ 0x704
│ │ │ │ -	stmiblt	r3, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	cmnphi	r4, #14614528	@ p-variant is OBSOLETE	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb982
│ │ │ │ +	vcge.s8	q12, q0, q10
│ │ │ │ +	ldrbtmi	r2, [r8], #1815	@ 0x717
│ │ │ │ +	ldmdblt	fp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	msrhi	SPSR_f, #14614528	@ 0xdf0000
│ │ │ │  	ldrcs	pc, [r7, -r0, asr #4]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb97c
│ │ │ │ -	vcgt.s8	q12, q0, q14
│ │ │ │ -	ldrbtmi	r2, [r8], #1815	@ 0x717
│ │ │ │ -	ldmdblt	r5!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	msrhi	SPSR_, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb974
│ │ │ │ +	vcgt.s8	q12, q0, q8
│ │ │ │ +	ldrbtmi	r2, [r8], #1946	@ 0x79a
│ │ │ │ +	stmdblt	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	cmpphi	r4, #14614528	@ p-variant is OBSOLETE	@ 0xdf0000
│ │ │ │  	ldrcs	pc, [sl, r0, asr #4]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb96e
│ │ │ │ -	vcge.s8	q12, q0, q4
│ │ │ │ -	ldrbtmi	r2, [r8], #1946	@ 0x79a
│ │ │ │ -	stmdblt	r7!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	movthi	pc, #51423	@ 0xc8df	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb966
│ │ │ │ +	vcgt.s8	q12, q0, q6
│ │ │ │ +	ldrbtmi	r3, [r8], #1907	@ 0x773
│ │ │ │ +	ldmdblt	pc, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^	@ <UNPREDICTABLE>
│ │ │ │ +	movthi	pc, #2271	@ 0x8df	@ <UNPREDICTABLE>
│ │ │ │  	ldrbcc	pc, [r3, -r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb960
│ │ │ │ -	vcgt.s8	q12, q0, q2
│ │ │ │ -	ldrbtmi	r3, [r8], #1907	@ 0x773
│ │ │ │ -	ldmdblt	r9, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	teqphi	r8, #14614528	@ p-variant is OBSOLETE	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb958
│ │ │ │ +	vcge.s8	d24, d0, d24
│ │ │ │ +	ldrbtmi	r4, [r8], #1867	@ 0x74b
│ │ │ │ +	ldmdblt	r1, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	msrhi	CPSR_fs, #14614528	@ 0xdf0000
│ │ │ │  	strbmi	pc, [fp, -r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb952
│ │ │ │ -	vcge.s8	d24, d0, d16
│ │ │ │ -	ldrbtmi	r4, [r8], #1867	@ 0x74b
│ │ │ │ -	stmdblt	fp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	msrhi	CPSR_s, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb94a
│ │ │ │ +	vcgt.s8	d24, d0, d20
│ │ │ │ +	ldrbtmi	r4, [r8], #1873	@ 0x751
│ │ │ │ +	stmdblt	r3, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	tstphi	r8, #14614528	@ p-variant is OBSOLETE	@ 0xdf0000
│ │ │ │  	ldrbmi	pc, [r1, -r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb944
│ │ │ │ -	vcge.s8	d24, d0, d12
│ │ │ │ -	ldrbtmi	r4, [r8], #1873	@ 0x751
│ │ │ │ -	ldmdblt	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	tstphi	r0, #14614528	@ p-variant is OBSOLETE	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb93c
│ │ │ │ +	vcge.s8	d24, d0, d0
│ │ │ │ +	ldrbtmi	r4, [r8], #1903	@ 0x76f
│ │ │ │ +	ldmdblt	r5!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	movwhi	pc, #18655	@ 0x48df	@ <UNPREDICTABLE>
│ │ │ │  	strbmi	pc, [pc, -r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb936
│ │ │ │ -	vcgt.s8	d24, d0, d8
│ │ │ │ -	ldrbtmi	r4, [r8], #1903	@ 0x76f
│ │ │ │ -	stmdblt	pc!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}	@ <UNPREDICTABLE>
│ │ │ │ -	rscshi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb92e
│ │ │ │ +	vqsub.s8	q12, q8, q14
│ │ │ │ +	ldrbtmi	r4, [r8], #1907	@ 0x773
│ │ │ │ +	stmdblt	r7!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	rscshi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │  	ldrbmi	pc, [r3, -r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb928
│ │ │ │ -	vqsub.s8	q12, q8, q10
│ │ │ │ -	ldrbtmi	r4, [r8], #1907	@ 0x773
│ │ │ │ -	stmdblt	r1!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	rschi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb920
│ │ │ │ +	vhsub.s8	q12, q8, q12
│ │ │ │ +	ldrbtmi	r4, [r8], #1998	@ 0x7ce
│ │ │ │ +	ldmdblt	r9, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	sbcshi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │  	strbmi	pc, [lr, r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb91a
│ │ │ │ -	vhsub.s8	q12, q8, q8
│ │ │ │ -	ldrbtmi	r4, [r8], #1998	@ 0x7ce
│ │ │ │ -	ldmdblt	r3, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	sbcshi	pc, r4, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb912
│ │ │ │ +	vst1.64	{d24-d27}, [pc :64], r4
│ │ │ │ +	ldrbtmi	r6, [r8], #1960	@ 0x7a8
│ │ │ │ +	stmdblt	fp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	sbchi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │  	strvs	pc, [r8, pc, asr #8]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb90c
│ │ │ │ -	vst1.64	{d24-d27}, [pc], ip
│ │ │ │ -	ldrbtmi	r6, [r8], #1960	@ 0x7a8
│ │ │ │ -	stmdblt	r5, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	sbchi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb904
│ │ │ │ +	vhsub.s8	q12, q8, q0
│ │ │ │ +	ldrbtmi	r5, [r8], #1866	@ 0x74a
│ │ │ │ +	ldmlt	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	adcshi	pc, r4, #14614528	@ 0xdf0000
│ │ │ │  	strbpl	pc, [sl, -r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8fe
│ │ │ │ -	vqsub.s8	d24, d16, d24
│ │ │ │ -	ldrbtmi	r5, [r8], #1866	@ 0x74a
│ │ │ │ -	ldmlt	r7!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	adchi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8f6
│ │ │ │ +	vhsub.s8	d24, d16, d28
│ │ │ │ +	ldrbtmi	r5, [r8], #1877	@ 0x755
│ │ │ │ +	stmialt	pc!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^	@ <UNPREDICTABLE>
│ │ │ │ +	adchi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │  	ldrbpl	pc, [r5, -r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8f0
│ │ │ │ -	vhsub.s8	d24, d16, d20
│ │ │ │ -	ldrbtmi	r5, [r8], #1877	@ 0x755
│ │ │ │ -	stmialt	r9!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	addshi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8e8
│ │ │ │ +	vqsub.s8	d24, d16, d8
│ │ │ │ +	ldrbtmi	r5, [r8], #1894	@ 0x766
│ │ │ │ +	stmialt	r1!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	addhi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │  	strbpl	pc, [r6, -r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8e2
│ │ │ │ -	vqsub.s8	d24, d16, d0
│ │ │ │ -	ldrbtmi	r5, [r8], #1894	@ 0x766
│ │ │ │ -	ldmlt	fp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	addhi	pc, r4, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8da
│ │ │ │ +	vhsub.s8	d24, d16, d4
│ │ │ │ +	ldrbtmi	r5, [r8], #1907	@ 0x773
│ │ │ │ +	ldmlt	r3, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	rsbshi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │  	ldrbpl	pc, [r3, -r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8d4
│ │ │ │ -	vqsub.s8	q12, q0, q14
│ │ │ │ -	ldrbtmi	r5, [r8], #1907	@ 0x773
│ │ │ │ -	stmialt	sp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	rsbshi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8cc
│ │ │ │ +	vqsub.s8	q12, q0, q8
│ │ │ │ +	ldrbtmi	r5, [r8], #1919	@ 0x77f
│ │ │ │ +	stmialt	r5, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	rsbhi	pc, r4, #14614528	@ 0xdf0000
│ │ │ │  	ldrbpl	pc, [pc, -r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8c6
│ │ │ │ -	vhsub.s8	q12, q0, q12
│ │ │ │ -	ldrbtmi	r5, [r8], #1919	@ 0x77f
│ │ │ │ -	ldmlt	pc!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}	@ <UNPREDICTABLE>
│ │ │ │ -	subshi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8be
│ │ │ │ +	vst1.16	{d24-d27}, [pc :64], ip
│ │ │ │ +	ldrbtmi	r6, [r8], #1970	@ 0x7b2
│ │ │ │ +	ldmlt	r7!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	subshi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │  	ldrvs	pc, [r2, pc, asr #8]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8b8
│ │ │ │ -	vst1.16	{d24-d27}, [pc :64], r4
│ │ │ │ -	ldrbtmi	r6, [r8], #1970	@ 0x7b2
│ │ │ │ -	ldmlt	r1!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	subhi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8b0
│ │ │ │ +	vhsub.s8	q12, q0, q4
│ │ │ │ +	ldrbtmi	r5, [r8], #1953	@ 0x7a1
│ │ │ │ +	stmialt	r9!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	eorshi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │  	strpl	pc, [r1, r0, asr #4]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb8aa
│ │ │ │ -	vhsub.s8	q12, q0, q0
│ │ │ │ -	ldrbtmi	r5, [r8], #1953	@ 0x7a1
│ │ │ │ -	stmialt	r3!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	eorshi	pc, r4, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb8a2
│ │ │ │ +	vqsub.s8	d24, d0, d20
│ │ │ │ +	ldrbtmi	r5, [r8], #1973	@ 0x7b5
│ │ │ │ +	ldmlt	fp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	eorhi	pc, r8, #14614528	@ 0xdf0000
│ │ │ │  	ldrpl	pc, [r5, r0, asr #4]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb89c
│ │ │ │ -	vhsub.s8	d24, d0, d28
│ │ │ │ -	ldrbtmi	r5, [r8], #1973	@ 0x7b5
│ │ │ │ -	ldmlt	r5, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	eorhi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb894
│ │ │ │ +	vhsub.s8	d24, d0, d16
│ │ │ │ +	ldrbtmi	r5, [r8], #2025	@ 0x7e9
│ │ │ │ +	stmlt	sp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	andshi	pc, r4, #14614528	@ 0xdf0000
│ │ │ │  	strbpl	pc, [r9, r0, asr #4]!	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb88e
│ │ │ │ -	vqsub.s8	d24, d0, d8
│ │ │ │ -	ldrbtmi	r5, [r8], #2025	@ 0x7e9
│ │ │ │ -	stmlt	r7, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	andhi	pc, ip, #14614528	@ 0xdf0000
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb886
│ │ │ │ +	vhsub.s8	d24, d0, d12
│ │ │ │ +	ldrbtmi	r6, [r8], #1803	@ 0x70b
│ │ │ │ +	ldmdalt	pc!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^	@ <UNPREDICTABLE>
│ │ │ │ +	andhi	pc, r0, #14614528	@ 0xdf0000
│ │ │ │  	strvs	pc, [fp, -r0, asr #4]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb880
│ │ │ │ -	vhsub.s8	d24, d0, d4
│ │ │ │ -	ldrbtmi	r6, [r8], #1803	@ 0x70b
│ │ │ │ -	ldmdalt	r9!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	ldrsbhi	pc, [r8, #143]!	@ 0x8f	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb878
│ │ │ │ +	vand	q12, q8, q12
│ │ │ │ +	ldrbtmi	r6, [r8], #1823	@ 0x71f
│ │ │ │ +	ldmdalt	r1!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	ldrdhi	pc, [ip, #143]!	@ 0x8f
│ │ │ │  	ldrvs	pc, [pc, -r0, asr #4]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb872
│ │ │ │ -	vand	q12, q8, q8
│ │ │ │ -	ldrbtmi	r6, [r8], #1823	@ 0x71f
│ │ │ │ -	stmdalt	fp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	ldrdhi	pc, [r4, #143]!	@ 0x8f
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb86a
│ │ │ │ +	vrhadd.s8	q12, q8, q10
│ │ │ │ +	ldrbtmi	r6, [r8], #1873	@ 0x751
│ │ │ │ +	stmdalt	r3!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	ldrsbhi	pc, [r8, #143]	@ 0x8f	@ <UNPREDICTABLE>
│ │ │ │  	ldrbvs	pc, [r1, -r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb864
│ │ │ │ -	vand	q12, q8, q6
│ │ │ │ -	ldrbtmi	r6, [r8], #1873	@ 0x751
│ │ │ │ -	ldmdalt	sp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	ldrsbhi	pc, [r0, #143]	@ 0x8f	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb85c
│ │ │ │ +	vst4.<illegal width 64>	{d24,d26,d28,d30}, [pc :64], r0
│ │ │ │ +	ldrbtmi	r6, [r8], #2007	@ 0x7d7
│ │ │ │ +	ldmdalt	r5, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	ldrdhi	pc, [r4, #143]	@ 0x8f
│ │ │ │  	ldrbvs	pc, [r7, pc, asr #8]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb856
│ │ │ │ -	vst4.<illegal width 64>	{d24,d26,d28,d30}, [pc], r8
│ │ │ │ -	ldrbtmi	r6, [r8], #2007	@ 0x7d7
│ │ │ │ -	stmdalt	pc, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^	@ <UNPREDICTABLE>
│ │ │ │ -			@ <UNDEFINED> instruction: 0x81bcf8df
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb84e
│ │ │ │ +	vand	d24, d16, d28
│ │ │ │ +	ldrbtmi	r7, [r8], #1812	@ 0x714
│ │ │ │ +	stmdalt	r7, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ +	asrshi	pc, pc	@ <illegal shifter operand>	@ <UNPREDICTABLE>
│ │ │ │  	ldrvc	pc, [r4, -r0, asr #4]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb848
│ │ │ │ -	vand	d24, d16, d20
│ │ │ │ -	ldrbtmi	r7, [r8], #1812	@ 0x714
│ │ │ │ -	stmdalt	r1, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}^
│ │ │ │ -	ldrdhi	pc, [r8, pc]!	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb840
│ │ │ │ +	vrhadd.s8	d24, d16, d24
│ │ │ │ +	ldrbtmi	r7, [r8], #1878	@ 0x756
│ │ │ │ +	ldmdalt	r9!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +			@ <UNDEFINED> instruction: 0x819cf8df
│ │ │ │  	ldrbvc	pc, [r6, -r0, asr #4]	@ <UNPREDICTABLE>
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb83a
│ │ │ │ -	vrhadd.s8	d24, d16, d16
│ │ │ │ -	ldrbtmi	r7, [r8], #1878	@ 0x756
│ │ │ │ -	ldmdalt	r3!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -			@ <UNDEFINED> instruction: 0x8194f8df
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb832
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf6408194
│ │ │ │ +	ldrbtmi	r0, [r8], #1839	@ 0x72f
│ │ │ │ +	stmdalt	fp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	ldrdhi	pc, [r8, pc]
│ │ │ │  	streq	pc, [pc, -r0, asr #12]!
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb82c
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf640818c
│ │ │ │ -	ldrbtmi	r0, [r8], #1839	@ 0x72f
│ │ │ │ -	stmdalt	r5!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	ldrdhi	pc, [r0, pc]
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb824
│ │ │ │ +	vst4.32	{d24,d26,d28,d30}, [pc], r0
│ │ │ │ +	ldrbtmi	r6, [r8], #1814	@ 0x716
│ │ │ │ +	ldmdalt	sp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ +	ldrsbhi	pc, [r4, #-143]!	@ 0xffffff71	@ <UNPREDICTABLE>
│ │ │ │  	ldrvs	pc, [r6, -pc, asr #8]
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfb81e
│ │ │ │ -	vst4.16	{d24,d26,d28,d30}, [pc :256], r8
│ │ │ │ -	ldrbtmi	r6, [r8], #1814	@ 0x716
│ │ │ │ -	ldmdalt	r7, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	ldrdhi	pc, [ip, #-143]!	@ 0xffffff71
│ │ │ │ -	ldrbtmi	r2, [r8], #1793	@ 0x701
│ │ │ │ -	ldmdalt	r1, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	ldrdhi	pc, [r4, #-143]!	@ 0xffffff71
│ │ │ │ -	ldrbtmi	r2, [r8], #1793	@ 0x701
│ │ │ │ -	stmdalt	fp, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	ldrsbhi	pc, [ip, #-143]	@ 0xffffff71	@ <UNPREDICTABLE>
│ │ │ │ -	ldrbtmi	r2, [r8], #1795	@ 0x703
│ │ │ │ -	stmdalt	r5, {r0, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ │ │ -	ldrsbhi	pc, [r4, #-143]	@ 0xffffff71	@ <UNPREDICTABLE>
│ │ │ │ -	ldrbtmi	r2, [r8], #1795	@ 0x703
│ │ │ │ -	svclt	0x00fff7fc
│ │ │ │ -	ldrdhi	pc, [ip, #-143]	@ 0xffffff71
│ │ │ │ -	ldrbtmi	r2, [r8], #1793	@ 0x701
│ │ │ │ -	svclt	0x00f9f7fc
│ │ │ │ -	ldrdhi	pc, [r4, #-143]	@ 0xffffff71
│ │ │ │ -	ldrbtmi	r2, [r8], #1793	@ 0x701
│ │ │ │ -	svclt	0x00f3f7fc
│ │ │ │ -	teqphi	ip, pc	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │ -	strbvc	pc, [ip, pc, asr #8]	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb816
│ │ │ │ +	strcs	r8, [r1, -ip, ror #2]
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb810
│ │ │ │ +	strcs	r8, [r1, -r4, ror #2]
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb80a
│ │ │ │ +	smlsdcs	r3, ip, r1, r8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fd44f8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfb804
│ │ │ │ +	smlsdcs	r3, r4, r1, r8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fc44f8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfbffe
│ │ │ │ +	strcs	r8, [r1, -ip, asr #2]
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fc44f8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfbff8
│ │ │ │ +	strcs	r8, [r1, -r4, asr #2]
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fc44f8
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf8dfbff2
│ │ │ │ +	vst4.8	{d24,d26,d28,d30}, [pc :256], ip
│ │ │ │ +	ldrbtmi	r7, [r8], #1996	@ 0x7cc
│ │ │ │ +	svclt	0x00ebf7fc
│ │ │ │ +	teqphi	r0, pc	@ <illegal shifter operand>	@ p-variant is OBSOLETE
│ │ │ │ +	ldrtmi	r2, [lr], -r1, lsl #14
│ │ │ │  			@ <UNDEFINED> instruction: 0xf7fc44f8
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf8dfbfec
│ │ │ │ -	smladxcs	r1, r4, r1, r8
│ │ │ │ -	ldrbtmi	r4, [r8], #1598	@ 0x63e
│ │ │ │ -	svclt	0x00e5f7fc
│ │ │ │ -	blmi	12dff14 <slow5_exit_condition@@Base+0x122db6c>
│ │ │ │ -	ldmpl	r3, {r1, r3, r4, r5, r6, sl, lr}^
│ │ │ │ -	blls	14e765c <slow5_exit_condition@@Base+0x14352b4>
│ │ │ │ -			@ <UNDEFINED> instruction: 0xf04f405a
│ │ │ │ -	andle	r0, r1, r0, lsl #6
│ │ │ │ -	b	feacb5e8 <slow5_exit_condition@@Base+0xfea19240>
│ │ │ │ -	pop	{r0, r2, r4, r6, ip, sp, pc}
│ │ │ │ -	svclt	0x00008ff0
│ │ │ │ +	bmi	12bd57c <slow5_exit_condition@@Base+0x120b1d4>
│ │ │ │ +	ldrbtmi	r4, [sl], #-2890	@ 0xfffff4b6
│ │ │ │ +	ldmdavs	sl, {r0, r1, r4, r6, r7, fp, ip, lr}
│ │ │ │ +	subsmi	r9, sl, r3, asr fp
│ │ │ │ +	movweq	pc, #79	@ 0x4f	@ <UNPREDICTABLE>
│ │ │ │ +			@ <UNDEFINED> instruction: 0xf7fad001
│ │ │ │ +	subslt	lr, r5, sl, lsr #21
│ │ │ │ +	svchi	0x00f0e8bd
│ │ │ │  	andeq	r0, r0, r8, asr r4
│ │ │ │ -			@ <UNDEFINED> instruction: 0x000761b8
│ │ │ │ -	andeq	r6, r7, sl, lsr #3
│ │ │ │ -	muleq	r7, ip, r1
│ │ │ │ -	andeq	r6, r7, lr, lsl #3
│ │ │ │ -	andeq	r6, r7, r0, lsl #3
│ │ │ │ -	andeq	r6, r7, r2, ror r1
│ │ │ │ -	andeq	r6, r7, r4, ror #2
│ │ │ │ -	andeq	r6, r7, r6, asr r1
│ │ │ │ -	andeq	r6, r7, r8, asr #2
│ │ │ │ -	andeq	r6, r7, sl, lsr r1
│ │ │ │ -	andeq	r6, r7, ip, lsr #2
│ │ │ │ -	andeq	r6, r7, lr, lsl r1
│ │ │ │ -	andeq	r6, r7, r0, lsl r1
│ │ │ │ -	andeq	r6, r7, r2, lsl #2
│ │ │ │ -	strdeq	r6, [r7], -r4
│ │ │ │ -	andeq	r6, r7, r6, ror #1
│ │ │ │ -	ldrdeq	r6, [r7], -r8
│ │ │ │ -	andeq	r6, r7, sl, asr #1
│ │ │ │ -	strheq	r6, [r7], -ip
│ │ │ │ -	andeq	r6, r7, lr, lsr #1
│ │ │ │ -	andeq	r6, r7, r0, lsr #1
│ │ │ │ -	muleq	r7, r2, r0
│ │ │ │ -	andeq	r6, r7, r4, lsl #1
│ │ │ │ -	andeq	r6, r7, r6, ror r0
│ │ │ │ -	andeq	r6, r7, r8, rrx
│ │ │ │ -	andeq	r6, r7, sl, asr r0
│ │ │ │ -	andeq	r6, r7, ip, asr #32
│ │ │ │ -	andeq	r6, r7, lr, lsr r0
│ │ │ │ -	andeq	r6, r7, r0, lsr r0
│ │ │ │ -	andeq	r6, r7, r2, lsr #32
│ │ │ │ -	andeq	r6, r7, r4, lsl r0
│ │ │ │ -	andeq	r6, r7, r6
│ │ │ │ -	strdeq	r5, [r7], -r8
│ │ │ │ -	andeq	r5, r7, sl, ror #31
│ │ │ │ -	ldrdeq	r5, [r7], -ip
│ │ │ │ -	andeq	r5, r7, lr, asr #31
│ │ │ │ -	andeq	r5, r7, r0, asr #31
│ │ │ │ -			@ <UNDEFINED> instruction: 0x00075fb2
│ │ │ │ -	andeq	r5, r7, r4, lsr #31
│ │ │ │ -	muleq	r7, r6, pc	@ <UNPREDICTABLE>
│ │ │ │ -	andeq	r5, r7, r8, lsl #31
│ │ │ │ -	andeq	r5, r7, sl, ror pc
│ │ │ │ -	andeq	r5, r7, ip, ror #30
│ │ │ │ -	andeq	r5, r7, lr, asr pc
│ │ │ │ -	andeq	r5, r7, r0, asr pc
│ │ │ │ -	andeq	r5, r7, r2, asr #30
│ │ │ │ -	andeq	r5, r7, r4, lsr pc
│ │ │ │ -	andeq	r5, r7, r6, lsr #30
│ │ │ │ -	andeq	r5, r7, r8, lsl pc
│ │ │ │ -	andeq	r5, r7, sl, lsl #30
│ │ │ │ -	strdeq	r5, [r7], -ip
│ │ │ │ -	andeq	r5, r7, lr, ror #29
│ │ │ │ -	andeq	r5, r7, r0, ror #29
│ │ │ │ -	ldrdeq	r5, [r7], -r2
│ │ │ │ -	andeq	r5, r7, r4, asr #29
│ │ │ │ -			@ <UNDEFINED> instruction: 0x00075eb6
│ │ │ │ -	andeq	r5, r7, r8, lsr #29
│ │ │ │ -	muleq	r7, sl, lr
│ │ │ │ -	strdeq	r5, [r7], -lr
│ │ │ │ -	strdeq	r5, [r7], -r2
│ │ │ │ -	andeq	r5, r7, r6, ror #17
│ │ │ │ +			@ <UNDEFINED> instruction: 0x000761b6
│ │ │ │ +	andeq	r6, r7, r8, lsr #3
│ │ │ │ +	muleq	r7, sl, r1
│ │ │ │ +	andeq	r6, r7, ip, lsl #3
│ │ │ │ +	andeq	r6, r7, lr, ror r1
│ │ │ │ +	andeq	r6, r7, r0, ror r1
│ │ │ │ +	andeq	r6, r7, r2, ror #2
│ │ │ │ +	andeq	r6, r7, r4, asr r1
│ │ │ │ +	andeq	r6, r7, r6, asr #2
│ │ │ │ +	andeq	r6, r7, r8, lsr r1
│ │ │ │ +	andeq	r6, r7, sl, lsr #2
│ │ │ │ +	andeq	r6, r7, ip, lsl r1
│ │ │ │ +	andeq	r6, r7, lr, lsl #2
│ │ │ │ +	andeq	r6, r7, r0, lsl #2
│ │ │ │ +	strdeq	r6, [r7], -r2
│ │ │ │ +	andeq	r6, r7, r4, ror #1
│ │ │ │ +	ldrdeq	r6, [r7], -r6	@ <UNPREDICTABLE>
│ │ │ │ +	andeq	r6, r7, r8, asr #1
│ │ │ │ +	strheq	r6, [r7], -sl
│ │ │ │ +	andeq	r6, r7, ip, lsr #1
│ │ │ │ +	muleq	r7, lr, r0
│ │ │ │ +	muleq	r7, r0, r0
│ │ │ │ +	andeq	r6, r7, r2, lsl #1
│ │ │ │ +	andeq	r6, r7, r4, ror r0
│ │ │ │ +	andeq	r6, r7, r6, rrx
│ │ │ │ +	andeq	r6, r7, r8, asr r0
│ │ │ │ +	andeq	r6, r7, sl, asr #32
│ │ │ │ +	andeq	r6, r7, ip, lsr r0
│ │ │ │ +	andeq	r6, r7, lr, lsr #32
│ │ │ │ +	andeq	r6, r7, r0, lsr #32
│ │ │ │ +	andeq	r6, r7, r2, lsl r0
│ │ │ │ +	andeq	r6, r7, r4
│ │ │ │ +	strdeq	r5, [r7], -r6
│ │ │ │ +	andeq	r5, r7, r8, ror #31
│ │ │ │  	ldrdeq	r5, [r7], -sl
│ │ │ │ -	andeq	r5, r7, lr, asr lr
│ │ │ │ -	andeq	r5, r7, r2, asr lr
│ │ │ │ -	andeq	r5, r7, r4, asr #28
│ │ │ │ -	andeq	r5, r7, r6, lsr lr
│ │ │ │ -	andeq	r2, sl, ip, asr #10
│ │ │ │ +	andeq	r5, r7, ip, asr #31
│ │ │ │ +			@ <UNDEFINED> instruction: 0x00075fbe
│ │ │ │ +			@ <UNDEFINED> instruction: 0x00075fb0
│ │ │ │ +	andeq	r5, r7, r2, lsr #31
│ │ │ │ +	muleq	r7, r4, pc	@ <UNPREDICTABLE>
│ │ │ │ +	andeq	r5, r7, r6, lsl #31
│ │ │ │ +	andeq	r5, r7, r8, ror pc
│ │ │ │ +	andeq	r5, r7, sl, ror #30
│ │ │ │ +	andeq	r5, r7, ip, asr pc
│ │ │ │ +	andeq	r5, r7, lr, asr #30
│ │ │ │ +	andeq	r5, r7, r0, asr #30
│ │ │ │ +	andeq	r5, r7, r2, lsr pc
│ │ │ │ +	andeq	r5, r7, r4, lsr #30
│ │ │ │ +	andeq	r5, r7, r6, lsl pc
│ │ │ │ +	andeq	r5, r7, r8, lsl #30
│ │ │ │ +	strdeq	r5, [r7], -sl
│ │ │ │ +	andeq	r5, r7, ip, ror #29
│ │ │ │ +	ldrdeq	r5, [r7], -lr
│ │ │ │ +	ldrdeq	r5, [r7], -r0
│ │ │ │ +	andeq	r5, r7, r2, asr #29
│ │ │ │ +			@ <UNDEFINED> instruction: 0x00075eb4
│ │ │ │ +	andeq	r5, r7, r6, lsr #29
│ │ │ │ +	muleq	r7, r8, lr
│ │ │ │ +	strdeq	r5, [r7], -ip
│ │ │ │ +	strdeq	r5, [r7], -r0
│ │ │ │ +	andeq	r5, r7, r4, ror #17
│ │ │ │ +	ldrdeq	r5, [r7], -r8
│ │ │ │ +	andeq	r5, r7, ip, asr lr
│ │ │ │ +	andeq	r5, r7, r0, asr lr
│ │ │ │ +	andeq	r5, r7, r2, asr #28
│ │ │ │ +	andeq	r5, r7, r4, lsr lr
│ │ │ │ +	andeq	r2, sl, sl, asr #10
│ │ │ │  	andeq	r0, r0, r4, lsl #8
│ │ │ │  
│ │ │ │  0000d718 <PyInit_pyslow5@@Base>:
│ │ │ │  	ldr	r0, [pc, #8]	@ (d724 <PyInit_pyslow5@@Base+0xc>)
│ │ │ │  	add	r0, pc
│ │ │ │  	addw	r0, r0, #3084	@ 0xc0c
│ │ │ │  	b.w	7908 <PyModuleDef_Init@plt>
│ │ │ ├── readelf --wide --decompress --hex-dump=.gnu_debuglink {}
│ │ │ │ @@ -1,7 +1,7 @@
│ │ │ │  
│ │ │ │  Hex dump of section '.gnu_debuglink':
│ │ │ │ -  0x00000000 66396337 35316630 62623131 65346162 f9c751f0bb11e4ab
│ │ │ │ -  0x00000010 61636232 66326663 33346336 36663463 acb2f2fc34c66f4c
│ │ │ │ -  0x00000020 31313830 62642e64 65627567 00000000 1180bd.debug....
│ │ │ │ -  0x00000030 f7487c83                            .H|.
│ │ │ │ +  0x00000000 34373163 33336235 66353338 64626636 471c33b5f538dbf6
│ │ │ │ +  0x00000010 31353135 64656339 30303539 39653137 1515dec900599e17
│ │ │ │ +  0x00000020 34333433 39322e64 65627567 00000000 434392.debug....
│ │ │ │ +  0x00000030 c4b18b7e                            ...~